Many semiconductor devices incorporate a dual-stress liner that blankets the various transistors of the devices and enhances their performance. In a dual-stress liner, a compressive stress liner is disposed over a region containing P-type field-effect transistors (PFETs) such that a compressive stress is induced on the PFET channels, and a tensile stress liner is disposed over a region containing N-type field-effect transistors (NFETs) such that a tensile stress is induced on the NFET channels. Thus, at least one boundary exists between the compressive and tensile stress liners.
There are various issues that should be dealt with when incorporating a dual-stress liner. For instance, at the boundary, the compressive and tensile stress liners may either overlap each other or there may be a gap between the two liners. Exact butting together of the two liners is neither a reliably repeatable nor practical structure to manufacture.
If the boundary has a gap between the two liners, then etching during manufacturing of through-holes in the stress liners intended for conductive contacts may also undesirably etch underlying silicide and silicon layers through the gap.
On the other hand, where the boundary is an overlapping boundary, then difficulties arise in simultaneously etching both the double-thickness overlap region and the single-thickness non-overlap regions of the stress layers. To effectively etch holes through the double layer thickness region, over-etching will typically occur in the single layer thickness regions. This over-etching may damage the device and reduce the yield of operational devices in a given batch. Moreover, since the majority of contacts are located in the single-layer thickness regions of the stress liners, the potential for device damage by over-etching in those regions is very high, thus even further negatively impacting the yield.